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Merge pull request #2523 from tomverbeure/define_synthesis 

Add -nosynthesis flag for read_verilog command
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Claire Xen 2021-03-01 18:00:48 +01:00 committed by GitHub
parent 527c681a2b 3a8eecebba
commit 004b780b8a
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 12 additions and 3 deletions
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15
frontends/verilog/verilog_frontend.cc
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@ -84,6 +84,9 @@ struct VerilogFrontend : public Frontend {
log(" enable support for SystemVerilog assertions and some Yosys extensions\n"); log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
log(" replace the implicit -D SYNTHESIS with -D FORMAL\n"); log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
log("\n"); log("\n");
log(" -nosynthesis\n");
log(" don't add implicit -D SYNTHESIS\n");
log("\n");
log(" -noassert\n"); log(" -noassert\n");
log(" ignore assert() statements\n"); log(" ignore assert() statements\n");
log("\n"); log("\n");
@ -225,8 +228,8 @@ struct VerilogFrontend : public Frontend {
log("the syntax of the code, rather than to rely on read_verilog for that.\n"); log("the syntax of the code, rather than to rely on read_verilog for that.\n");
log("\n"); log("\n");
log("Depending on if read_verilog is run in -formal mode, either the macro\n"); log("Depending on if read_verilog is run in -formal mode, either the macro\n");
log("SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog\n"); log("SYNTHESIS or FORMAL is defined automatically, unless -nosynthesis is used.\n");
log("always defines the macro YOSYS.\n"); log("In addition, read_verilog always defines the macro YOSYS.\n");
log("\n"); log("\n");
log("See the Yosys README file for a list of non-standard Verilog features\n"); log("See the Yosys README file for a list of non-standard Verilog features\n");
log("supported by the Yosys Verilog front-end.\n"); log("supported by the Yosys Verilog front-end.\n");
@ -255,6 +258,7 @@ struct VerilogFrontend : public Frontend {
bool flag_defer = false; bool flag_defer = false;
bool flag_noblackbox = false; bool flag_noblackbox = false;
bool flag_nowb = false; bool flag_nowb = false;
bool flag_nosynthesis = false;
define_map_t defines_map; define_map_t defines_map;
std::list<std::string> include_dirs; std::list<std::string> include_dirs;
@ -282,6 +286,10 @@ struct VerilogFrontend : public Frontend {
formal_mode = true; formal_mode = true;
continue; continue;
} }
if (arg == "-nosynthesis") {
flag_nosynthesis = true;
continue;
}
if (arg == "-noassert") { if (arg == "-noassert") {
noassert_mode = true; noassert_mode = true;
continue; continue;
@ -447,7 +455,8 @@ struct VerilogFrontend : public Frontend {
break; break;
} }
defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1"); if (formal_mode || !flag_nosynthesis)
defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);