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38 lines
754 B
Plaintext
38 lines
754 B
Plaintext
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log -header "Test simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module muldiv_const_ok (
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input wire [31:0] a,
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output wire [63:0] y
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);
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assign y = (a * 5140) / (257 * 2);
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endmodule
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EOF
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check -assert
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equiv_opt -assert peepopt ;;;
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design -load postopt
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select -assert-any t:$mul # assert mult
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log -pop
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log -header "Test negative case where div is kept"
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log -push
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design -reset
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read_verilog <<EOF
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module muldiv_const_ko (
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input wire signed [31:0] a,
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output wire signed [63:0] y,
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output wire probe
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);
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wire [44:0] tmp = (a * 5140);
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assign probe = tmp[44];
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assign y = tmp[43:0] / (257 * 2);
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endmodule
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EOF
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check -assert
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equiv_opt -assert peepopt ;;;
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design -load postopt
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select -assert-any t:$div # assert div
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log -pop
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