mirror of https://github.com/YosysHQ/yosys.git
64 lines
1.9 KiB
C++
64 lines
1.9 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/macc.h"
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struct AlumaccWorker
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{
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RTLIL::Module *module;
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AlumaccWorker(RTLIL::Module *module) : module(module)
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{
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}
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};
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struct AlumaccPass : public Pass {
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AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" alumacc [selection]\n");
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log("\n");
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log("This pass translates arithmetic operations $add, $mul, $lt, etc. to $alu and\n");
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log("$macc cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing ALUMACC pass (create $alu and $macc cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-foobar") {
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// foobar_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules()) {
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AlumaccWorker worker(mod);
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}
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}
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} AlumaccPass;
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