mirror of https://github.com/YosysHQ/yosys.git
99 lines
2.2 KiB
Plaintext
99 lines
2.2 KiB
Plaintext
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read_verilog <<EOT
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(* techmap_celltype = "$_DFF_P_" *)
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module ffmap(...);
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input D;
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input C;
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output Q;
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parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
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ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
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wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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endmodule
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EOT
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design -stash map
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read_verilog <<EOT
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(* techmap_celltype = "$_DFF_P_" *)
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module ffmap(...);
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input D;
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input C;
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output Q;
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parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
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ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
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wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
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endmodule
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EOT
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design -stash map_noremove
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read_verilog <<EOT
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module ffbb (...);
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parameter [0:0] INIT = 1'bx;
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input D, C;
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output Q;
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endmodule
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module top(...);
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input clk;
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input d;
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output reg q0 = 0;
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output reg q1 = 1;
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output reg qx;
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always @(posedge clk) begin
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q0 <= d;
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q1 <= d;
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qx <= d;
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end
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endmodule
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EOT
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design -save ref
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hierarchy -auto-top
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proc
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simplemap
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techmap -map %map
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clean
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# Make sure the parameter was used properly.
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select -assert-count 2 top/t:ffbb
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select -set ff0 top/w:q0 %ci t:ffbb %i
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select -set ffx top/w:qx %ci t:ffbb %i
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select -assert-count 1 @ff0
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select -assert-count 1 @ffx
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select -assert-count 1 @ff0 r:INIT=1'b0 %i
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select -assert-count 1 @ffx r:INIT=1'bx %i
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select -assert-count 0 top/w:q1 %ci t:ffbb %i
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# Make sure the init values are dropped from the wires iff mapping was performed.
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select -assert-count 0 top/w:q0 a:init %i
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select -assert-count 1 top/w:q1 a:init=1'b1 %i
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select -assert-count 0 top/w:qx a:init %i
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design -load ref
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hierarchy -auto-top
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proc
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simplemap
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techmap -map %map_noremove
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clean
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# Make sure the parameter was used properly.
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select -assert-count 2 top/t:ffbb
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select -set ff0 top/w:q0 %ci t:ffbb %i
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select -set ffx top/w:qx %ci t:ffbb %i
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select -assert-count 1 @ff0
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select -assert-count 1 @ffx
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select -assert-count 1 @ff0 r:INIT=1'b0 %i
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select -assert-count 1 @ffx r:INIT=1'bx %i
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select -assert-count 0 top/w:q1 %ci t:ffbb %i
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# Make sure the init values are not dropped from the wires.
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select -assert-count 1 top/w:q0 a:init=1'b0 %i
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select -assert-count 1 top/w:q1 a:init=1'b1 %i
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select -assert-count 0 top/w:qx a:init %i
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