mirror of https://github.com/YosysHQ/yosys.git
10 lines
125 B
Verilog
10 lines
125 B
Verilog
|
`include "common_sim.vh"
|
||
|
|
`include "ccu2c_sim.vh"
|
||
|
|
|
||
|
|
`ifndef NO_INCLUDES
|
||
|
|
|
||
|
|
`include "cells_ff.vh"
|
||
|
|
`include "cells_io.vh"
|
||
|
|
|
||
|
|
`endif
|