mirror of https://github.com/YosysHQ/yosys.git
17 lines
276 B
Verilog
17 lines
276 B
Verilog
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module uut_arrays01(clock, we, addr, wr_data, rd_data);
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input clock, we;
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input [3:0] addr, wr_data;
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output [3:0] rd_data;
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reg [3:0] rd_data;
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reg [3:0] memory [15:0];
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always @(posedge clock) begin
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if (we)
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memory[addr] <= wr_data;
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rd_data <= memory[addr];
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end
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endmodule
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