mirror of https://github.com/YosysHQ/yosys.git
9 lines
142 B
Verilog
9 lines
142 B
Verilog
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module uut(in1, in2, in3, out1, out2);
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input [8:0] in1, in2, in3;
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output [8:0] out1, out2;
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assign out1 = in1 + in2 + (in3 >> 4);
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endmodule
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