yosys/tests/asicworld/code_hdl_models_t_gate_swit...

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2013-01-05 04:13:26 -06:00
module t_gate_switch (L,R,nC,C);
inout L;
inout R;
input nC;
input C;
//Syntax: keyword unique_name (drain. source, gate);
pmos p1 (L,R,nC);
nmos p2 (L,R,C);
endmodule