mirror of https://github.com/YosysHQ/yosys.git
15 lines
252 B
Plaintext
15 lines
252 B
Plaintext
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read_verilog abc9.v
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proc
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design -save gold
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abc9 -lut 4
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check
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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