mirror of https://github.com/YosysHQ/yosys.git
15 lines
188 B
Verilog
15 lines
188 B
Verilog
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module always_full_tb;
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reg clk = 0;
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wire fin;
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always_full uut (.clk(clk), .fin(fin));
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always begin
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#1 clk <= ~clk;
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if (fin) $finish;
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end
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endmodule
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