2019-04-29 06:02:05 -05:00
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pattern ice40_dsp
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2019-01-13 03:57:11 -06:00
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state <SigBit> clock
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2019-07-19 12:57:32 -05:00
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state <bool> clock_pol
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2019-01-13 10:03:58 -06:00
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state <SigSpec> sigA sigB sigY sigS
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2019-07-19 12:57:32 -05:00
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state <SigSpec> sigYused
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2019-01-13 10:03:58 -06:00
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state <Cell*> addAB muxAB
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2019-01-11 07:02:16 -06:00
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match mul
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2019-07-18 17:38:28 -05:00
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select mul->type.in($mul, $__MUL16X16)
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2019-01-11 07:02:16 -06:00
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select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
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select GetSize(mul->getPort(\Y)) > 10
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endmatch
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match ffA
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select ffA->type.in($dff)
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2019-07-19 12:57:32 -05:00
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filter !port(mul, \A).remove_const().empty()
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filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
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2019-01-11 07:02:16 -06:00
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optional
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endmatch
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2019-07-19 12:57:32 -05:00
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code sigA clock clock_pol
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2019-01-11 07:02:16 -06:00
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sigA = port(mul, \A);
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2019-01-13 10:03:58 -06:00
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if (ffA) {
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2019-01-11 07:02:16 -06:00
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clock = port(ffA, \CLK).as_bit();
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clock_pol = param(ffA, \CLK_POLARITY).as_bool();
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2019-07-19 22:25:28 -05:00
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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2019-01-11 07:02:16 -06:00
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}
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endcode
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match ffB
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select ffB->type.in($dff)
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2019-07-19 12:57:32 -05:00
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filter !port(mul, \B).remove_const().empty()
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filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
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2019-01-11 07:02:16 -06:00
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optional
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endmatch
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2019-07-19 12:57:32 -05:00
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code sigB clock clock_pol
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2019-01-11 07:02:16 -06:00
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sigB = port(mul, \B);
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2019-01-13 10:03:58 -06:00
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if (ffB) {
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2019-01-11 07:02:16 -06:00
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SigBit c = port(ffB, \CLK).as_bit();
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bool cp = param(ffB, \CLK_POLARITY).as_bool();
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2019-07-19 12:57:32 -05:00
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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2019-01-11 07:02:16 -06:00
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reject;
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clock = c;
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clock_pol = cp;
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2019-07-19 22:25:28 -05:00
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sigB.replace(port(ffB, \Q), port(ffB, \D));
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2019-01-11 07:02:16 -06:00
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}
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endcode
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2019-07-19 12:57:32 -05:00
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// Extract the bits of Y that actually have a consumer
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// (as opposed to being a sign extension)
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code sigY sigYused
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sigY = port(mul, \Y);
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int i;
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for (i = GetSize(sigY); i > 0; i--)
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if (nusers(sigY[i-1]) > 1)
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break;
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2019-07-19 22:25:28 -05:00
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sigYused = sigY.extract(0, i);
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2019-07-19 12:57:32 -05:00
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endcode
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2019-01-11 07:02:16 -06:00
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match ffY
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select ffY->type.in($dff)
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2019-01-13 03:57:11 -06:00
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select nusers(port(ffY, \D)) == 2
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2019-07-19 12:57:32 -05:00
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filter param(ffY, \WIDTH).as_int() >= GetSize(sigYused)
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filter includes(port(ffY, \D).to_sigbit_set(), sigYused.to_sigbit_set())
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2019-01-11 07:02:16 -06:00
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optional
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endmatch
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2019-07-19 12:57:32 -05:00
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code clock clock_pol sigY
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2019-01-13 10:03:58 -06:00
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if (ffY) {
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2019-07-19 12:57:32 -05:00
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sigY.replace(port(ffY, \D), port(ffY, \Q));
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2019-01-11 07:02:16 -06:00
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SigBit c = port(ffY, \CLK).as_bit();
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bool cp = param(ffY, \CLK_POLARITY).as_bool();
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2019-07-19 12:57:32 -05:00
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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2019-01-11 07:02:16 -06:00
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reject;
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clock = c;
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clock_pol = cp;
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}
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endcode
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2019-01-13 10:03:58 -06:00
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match addA
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2019-02-17 08:35:48 -06:00
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select addA->type.in($add)
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2019-01-13 10:03:58 -06:00
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select nusers(port(addA, \A)) == 2
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index <SigSpec> port(addA, \A) === sigY
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optional
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endmatch
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match addB
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if !addA
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select addB->type.in($add, $sub)
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select nusers(port(addB, \B)) == 2
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index <SigSpec> port(addB, \B) === sigY
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optional
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endmatch
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code addAB sigS
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if (addA) {
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addAB = addA;
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sigS = port(addA, \B);
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}
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if (addB) {
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addAB = addB;
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sigS = port(addB, \A);
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}
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2019-02-20 04:18:19 -06:00
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if (addAB) {
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int natural_mul_width = GetSize(sigA) + GetSize(sigB);
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int actual_mul_width = GetSize(sigY);
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int actual_acc_width = GetSize(sigS);
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if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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reject;
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if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
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reject;
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}
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2019-01-13 10:03:58 -06:00
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endcode
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match muxA
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if addAB
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select muxA->type.in($mux)
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select nusers(port(muxA, \A)) == 2
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index <SigSpec> port(muxA, \A) === port(addAB, \Y)
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optional
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endmatch
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match muxB
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if addAB
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if !muxA
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select muxB->type.in($mux)
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select nusers(port(muxB, \B)) == 2
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index <SigSpec> port(muxB, \B) === port(addAB, \Y)
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optional
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endmatch
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code muxAB
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muxAB = addAB;
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if (muxA)
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muxAB = muxA;
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if (muxB)
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muxAB = muxB;
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endcode
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match ffS
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if muxAB
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select ffS->type.in($dff)
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select nusers(port(ffS, \D)) == 2
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index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
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index <SigSpec> port(ffS, \Q) === sigS
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endmatch
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2019-02-17 08:35:48 -06:00
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2019-07-19 12:57:32 -05:00
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code clock clock_pol
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2019-02-17 08:35:48 -06:00
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if (ffS) {
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SigBit c = port(ffS, \CLK).as_bit();
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bool cp = param(ffS, \CLK_POLARITY).as_bool();
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2019-07-19 12:57:32 -05:00
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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2019-02-17 08:35:48 -06:00
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reject;
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clock = c;
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clock_pol = cp;
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}
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endcode
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