mirror of https://github.com/YosysHQ/yosys.git
34 lines
616 B
Verilog
34 lines
616 B
Verilog
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module top(w, x, y, z);
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function [11:0] func;
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input reg [2:0] x;
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input reg [2:0] y;
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begin
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x = x * (y + 1);
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begin : foo
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reg [2:0] y;
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y = x + 1;
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begin : bar
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reg [2:0] x;
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x = y + 1;
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begin : blah
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reg [2:0] y;
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y = x + 1;
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func[2:0] = y;
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end
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func[5:3] = x;
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end
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func[8:6] = y;
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end
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func[11:9] = x;
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end
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endfunction
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output wire [func(2, 3) - 1:0] w;
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output wire [func(1, 3) - 1:0] x;
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output wire [func(3, 1) - 1:0] y;
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output wire [func(5, 2) - 1:0] z;
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assign w = 1'sb1;
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assign x = 1'sb1;
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assign y = 1'sb1;
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assign z = 1'sb1;
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endmodule
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