mirror of https://github.com/YosysHQ/yosys.git
24 lines
492 B
Verilog
24 lines
492 B
Verilog
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module bar(clk, rst, inp_a, inp_b, out);
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input wire clk;
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input wire rst;
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input wire [7:0] inp_a;
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input wire [7:0] inp_b;
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output reg [7:0] out;
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always @(posedge clk)
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if (rst) out <= 0;
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else out <= inp_a + (* ripple_adder *) inp_b;
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endmodule
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module foo(clk, rst, inp_a, inp_b, out);
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input wire clk;
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input wire rst;
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input wire [7:0] inp_a;
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input wire [7:0] inp_b;
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output wire [7:0] out;
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bar bar_instance (clk, rst, inp_a, inp_b, out);
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endmodule
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