mirror of https://github.com/YosysHQ/yosys.git
13 lines
219 B
Plaintext
13 lines
219 B
Plaintext
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read_verilog <<EOT
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module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
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wire [7:0] P = A * B;
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wire signed [7:0] SP = P;
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wire signed [3:0] SB = B;
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assign Y = SP / SB;
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endmodule
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EOT
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equiv_opt -assert peepopt
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