mirror of https://github.com/YosysHQ/yosys.git
29 lines
617 B
Verilog
29 lines
617 B
Verilog
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-rd-clk \clk
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module ram2 (input clk,
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input sel,
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input we,
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input [SIZE-1:0] adr,
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input [63:0] dat_i,
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output reg [63:0] dat_o);
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parameter SIZE = 5; // Address size
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reg [63:0] mem [0:(1 << SIZE)-1];
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integer i;
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initial begin
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for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
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mem[i] <= 0;
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end
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always @(posedge clk)
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if (sel) begin
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if (~we)
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dat_o <= mem[adr];
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else
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mem[adr] <= dat_i;
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end
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endmodule
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