mirror of https://github.com/YosysHQ/yosys.git
19 lines
345 B
Verilog
19 lines
345 B
Verilog
|
module addbit (
|
||
|
|
a,
|
||
|
|
b,
|
||
|
|
ci,
|
||
|
|
sum,
|
||
|
|
co);
|
||
|
|
input a;
|
||
|
|
input b;
|
||
|
|
input ci;
|
||
|
|
output sum;
|
||
|
|
output co;
|
||
|
|
wire a;
|
||
|
|
wire b;
|
||
|
|
wire ci;
|
||
|
|
wire sum;
|
||
|
|
wire co;
|
||
|
|
|
||
|
|
endmodule
|