yosys/manual/PRESENTATION_ExSyn/opt_04.v

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2014-02-02 15:26:26 -06:00
module test(input CLK, ARST,
output [7:0] Q1, Q2, Q3);
wire NO_CLK = 0;
always @(posedge CLK, posedge ARST)
if (ARST)
Q1 <= 42;
always @(posedge NO_CLK, posedge ARST)
if (ARST)
Q2 <= 42;
else
Q2 <= 23;
always @(posedge CLK)
Q3 <= 42;
endmodule