mirror of https://github.com/YosysHQ/yosys.git
7 lines
119 B
Verilog
7 lines
119 B
Verilog
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module test(a, b, c, d, y);
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input [15:0] a, b;
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input [31:0] c, d;
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output [31:0] y;
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assign y = a * b + c + d;
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endmodule
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