mirror of https://github.com/YosysHQ/yosys.git
93 lines
3.7 KiB
Coq
93 lines
3.7 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Mixcolumns for 8 bit ////
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//// ////
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//// This file is part of the SystemC AES ////
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//// ////
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//// Description: ////
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//// Mixcolum for a byte ////
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//// ////
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//// Generated automatically using SystemC to Verilog translator ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: byte_mixcolum.v,v $
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// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo
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// First import
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//
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module byte_mixcolum(a,b,c,d,outx,outy);
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input [7:0] a,b,c,d;
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output [7:0] outx, outy;
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reg [7:0] outx, outy;
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function [7:0] xtime;
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input [7:0] in;
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reg [3:0] xtime_t;
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begin
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xtime[7:5] = in[6:4];
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xtime_t[3] = in[7];
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xtime_t[2] = in[7];
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xtime_t[1] = 0;
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xtime_t[0] = in[7];
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xtime[4:1] =xtime_t^in[3:0];
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xtime[0] = in[7];
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end
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endfunction
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reg [7:0] w1,w2,w3,w4,w5,w6,w7,w8,outx_var;
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always @ (a, b, c, d)
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begin
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w1 = a ^b;
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w2 = a ^c;
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w3 = c ^d;
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w4 = xtime(w1);
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w5 = xtime(w3);
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w6 = w2 ^w4 ^w5;
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w7 = xtime(w6);
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w8 = xtime(w7);
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outx_var = b^w3^w4;
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outx=outx_var;
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outy=w8^outx_var;
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end
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endmodule
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