mirror of https://github.com/YosysHQ/yosys.git
8 lines
148 B
Coq
8 lines
148 B
Coq
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module test(input in, output out);
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//intermediate buffers should be removed
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wire w1, w2;
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assign w1 = in;
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assign w2 = w1;
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assign out = w2;
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endmodule
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