mirror of https://github.com/YosysHQ/yosys.git
19 lines
456 B
Coq
19 lines
456 B
Coq
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//-----------------------------------------------------
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// Design Name : mux_2to1_gates
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// File Name : mux_2to1_gates.v
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// Function : 2:1 Mux using Gate Primitives
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module mux_2to1_gates(a,b,sel,y);
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input a,b,sel;
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output y;
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wire sel,a_sel,b_sel;
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not U_inv (inv_sel,sel);
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and U_anda (asel,a,inv_sel),
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U_andb (bsel,b,sel);
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or U_or (y,asel,bsel);
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endmodule
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