mirror of https://github.com/YosysHQ/yosys.git
32 lines
487 B
Plaintext
32 lines
487 B
Plaintext
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read_rtlil <<EOT
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autoidx 1
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module \top
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wire input 1 \clk
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wire input 2 \rst
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wire input 3 \a_r
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wire input 4 \a_n
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wire input 5 \b_n
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wire \a
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wire \b
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process $proc
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sync high \rst
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update \a \a_r
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update \b \b
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sync posedge \clk
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update \a \a_n
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update \b \b_n
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end
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end
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EOT
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proc_dff
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proc_clean
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# Processes should have been converted to one aldff and one dff
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select -assert-none p:*
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select -assert-count 1 t:$aldff
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select -assert-count 1 t:$dff
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