mirror of https://github.com/YosysHQ/yosys.git
52 lines
1.7 KiB
Plaintext
52 lines
1.7 KiB
Plaintext
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# ISC License
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#
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# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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# regular unsigned multiply
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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synth_microchip -family polarfire -noiopad
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MACC_PA
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select -assert-none t:MACC_PA %% t:* %D
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# regular signed multiply
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design -reset
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read_verilog <<EOT
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module signed_mult(
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input signed [17:0] in_A,
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input signed [17:0] in_B,
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output signed [35:0] out_Y
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);
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assign out_Y = in_A * in_B;
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endmodule
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EOT
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synth_microchip -top signed_mult -family polarfire -noiopad
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select -assert-count 1 t:MACC_PA
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select -assert-none t:MACC_PA %% t:* %D
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# wide multiply
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 30 -set Y_WIDTH 16 -set A_WIDTH 46
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hierarchy -top top
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proc
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synth_microchip -family polarfire -noiopad
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MACC_PA
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select -assert-none t:MACC_PA %% t:* %D
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