mirror of https://github.com/YosysHQ/yosys.git
48 lines
2.4 KiB
ReStructuredText
48 lines
2.4 KiB
ReStructuredText
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.. role:: verilog(code)
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:language: Verilog
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Multiplexers
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------------
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Multiplexers are generated by the Verilog HDL frontend for ``?:``-expressions.
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Multiplexers are also generated by the proc pass to map the decision trees from
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RTLIL::Process objects to logic.
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The simplest multiplexer cell type is `$mux`. Cells of this type have a
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``WITDH`` parameter and data inputs ``A`` and ``B`` and a data output ``Y``, all
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of the specified width. This cell also has a single bit control input ``S``. If
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``S`` is 0 the value from the input ``A`` is sent to the output, if it is 1 the
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value from the ``B`` input is sent to the output. So the `$mux` cell implements
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the function :verilog:`Y = S ? B : A`.
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The `$pmux` cell is used to multiplex between many inputs using a one-hot select
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signal. Cells of this type have a ``WIDTH`` and a ``S_WIDTH`` parameter and
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inputs ``A``, ``B``, and ``S`` and an output ``Y``. The ``S`` input is
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``S_WIDTH`` bits wide. The ``A`` input and the output are both ``WIDTH`` bits
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wide and the ``B`` input is ``WIDTH*S_WIDTH`` bits wide. When all bits of ``S``
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are zero, the value from ``A`` input is sent to the output. If the :math:`n`\
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'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of
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the ``B`` input is sent to the output. When more than one bit from ``S`` is set
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the output is undefined. Cells of this type are used to model "parallel cases"
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(defined by using the ``parallel_case`` attribute or detected by an
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optimization).
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The `$tribuf` cell is used to implement tristate logic. Cells of this type have
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a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A``
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input and ``Y`` output are ``WIDTH`` bits wide, and the ``EN`` input is one bit
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wide. When ``EN`` is 0, the output is not driven. When ``EN`` is 1, the value
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from ``A`` input is sent to the ``Y`` output. Therefore, the `$tribuf` cell
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implements the function :verilog:`Y = EN ? A : 'bz`.
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Behavioural code with cascaded if-then-else- and case-statements usually results
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in trees of multiplexer cells. Many passes (from various optimizations to FSM
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extraction) heavily depend on these multiplexer trees to understand dependencies
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between signals. Therefore optimizations should not break these multiplexer
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trees (e.g. by replacing a multiplexer between a calculated signal and a
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constant zero with an `$and` gate).
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.. autocellgroup:: mux
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:members:
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:source:
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:linenos:
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