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efc3c13ec3
yosys
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tests
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svinterfaces
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run-test.sh
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Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 14:27:04 -05:00
#/bin/bash -e
./runone.sh svinterface1
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 04:58:25 -05:00
./runone.sh svinterface_at_top