mirror of https://github.com/YosysHQ/yosys.git
36 lines
595 B
Verilog
36 lines
595 B
Verilog
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(* abc9_box *)
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module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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endspecify
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assign Y = $signed(A) * $signed(B);
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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endspecify
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assign Y = $signed(A) * $signed(B);
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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endspecify
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assign Y = $signed(A) * $signed(B);
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endmodule
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