mirror of https://github.com/YosysHQ/yosys.git
61 lines
1.7 KiB
Verilog
61 lines
1.7 KiB
Verilog
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//-----------------------------------------------------
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// Design Name : cam
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// File Name : cam.v
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// Function : CAM
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module cam (
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clk , // Cam clock
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cam_enable , // Cam enable
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cam_data_in , // Cam data to match
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cam_hit_out , // Cam match has happened
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cam_addr_out // Cam output address
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);
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parameter ADDR_WIDTH = 8;
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parameter DEPTH = 1 << ADDR_WIDTH;
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//------------Input Ports--------------
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input clk;
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input cam_enable;
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input [DEPTH-1:0] cam_data_in;
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//----------Output Ports--------------
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output cam_hit_out;
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output [ADDR_WIDTH-1:0] cam_addr_out;
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//------------Internal Variables--------
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reg [ADDR_WIDTH-1:0] cam_addr_out;
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reg cam_hit_out;
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reg [ADDR_WIDTH-1:0] cam_addr_combo;
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reg cam_hit_combo;
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reg found_match;
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integer i;
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//-------------Code Starts Here-------
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always @(cam_data_in) begin
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cam_addr_combo = {ADDR_WIDTH{1'b0}};
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found_match = 1'b0;
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cam_hit_combo = 1'b0;
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for (i=0; i<DEPTH; i=i+1) begin
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if (cam_data_in[i] && !found_match) begin
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found_match = 1'b1;
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cam_hit_combo = 1'b1;
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cam_addr_combo = i;
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end else begin
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found_match = found_match;
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cam_hit_combo = cam_hit_combo;
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cam_addr_combo = cam_addr_combo;
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end
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end
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end
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// Register the outputs
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always @(posedge clk) begin
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if (cam_enable) begin
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cam_hit_out <= cam_hit_combo;
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cam_addr_out <= cam_addr_combo;
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end else begin
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cam_hit_out <= 1'b0;
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cam_addr_out <= {ADDR_WIDTH{1'b0}};
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end
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end
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endmodule
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