yosys/tests/verilog/func_upto.ys

read_verilog -sv func_upto.sv
hierarchy -top top
proc
flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -prove-asserts -enable_undef
verilog: fix const func eval with upto variables 2022-01-12 00:51:08 -06:00			`read_verilog -sv func_upto.sv`
			`hierarchy -top top`
			`proc`
			`flatten`
			`opt -full`
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. 2024-01-22 10:44:05 -06:00			`async2sync`
verilog: fix const func eval with upto variables 2022-01-12 00:51:08 -06:00			`select -module top`
			`sat -verify -seq 1 -prove-asserts -enable_undef`