mirror of https://github.com/YosysHQ/yosys.git
18 lines
350 B
Plaintext
18 lines
350 B
Plaintext
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logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1
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read_verilog -sv <<EOT
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interface intf;
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logic x;
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assign x = 1;
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modport m(input x);
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endinterface
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module mod(intf.m i);
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wire x;
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assign x = i.x;
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wire i;
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endmodule
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module top;
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intf i();
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mod m(i);
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endmodule
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EOT
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