mirror of https://github.com/YosysHQ/yosys.git
14 lines
284 B
Verilog
14 lines
284 B
Verilog
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module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
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input CLK, WR_DATA, WR_EN;
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input [3:0] RD_ADDR, WR_ADDR;
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output reg RD_DATA;
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reg [15:0] memory;
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always @(posedge CLK) begin
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if (WR_EN)
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memory[WR_ADDR] <= WR_DATA;
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RD_DATA <= memory[RD_ADDR];
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end
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endmodule
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