mirror of https://github.com/YosysHQ/yosys.git
12 lines
188 B
Verilog
12 lines
188 B
Verilog
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module uut_localparam_attr (I, O);
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(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
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localparam WIDTH = 1;
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input wire [WIDTH-1:0] I;
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output wire [WIDTH-1:0] O;
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assign O = I;
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endmodule
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