mirror of https://github.com/YosysHQ/yosys.git
17 lines
250 B
Verilog
17 lines
250 B
Verilog
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module top(input a, b, output o);
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assign o = a & b;
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endmodule
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(* blackbox *)
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module bb(input a, b, output o);
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assign o = a | b;
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specify
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(a => o) = 1;
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endspecify
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endmodule
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(* whitebox *)
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module wb(input a, b, output o);
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assign o = a ^ b;
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endmodule
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