mirror of https://github.com/YosysHQ/yosys.git
65 lines
897 B
Plaintext
65 lines
897 B
Plaintext
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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(* keep *)
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\$_DFF_P_ ffo (
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.C(clk),
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.D(i),
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.Q(o)
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);
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\$_DFF_P_ ffp (
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.C(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 1 a:keep
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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\$_DFF_P_ ffo (
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.C(clk),
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.D(i),
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.Q(o)
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);
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(* keep *)
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\$_DFF_P_ ffp (
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.C(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 1 a:keep
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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(* keep *)
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\$_DFF_P_ ffo (
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.C(clk),
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.D(i),
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.Q(o)
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);
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(* keep *)
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\$_DFF_P_ ffp (
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.C(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 2 a:keep
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