2024-11-04 17:36:31 -06:00
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read_rtlil <<EOT
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2021-08-07 17:33:31 -05:00
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module \mod
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wire input 1 \clk
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attribute \init 2'00
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wire width 2 $q1
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attribute \init 2'00
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wire width 2 $q2
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wire output 2 width 4 \q
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cell $dff $ff1
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parameter \CLK_POLARITY 1'1
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parameter \WIDTH 1
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connect \CLK \clk
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connect \D 1'0
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connect \Q $q1 [0]
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end
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cell $dff $ff2
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parameter \CLK_POLARITY 1'1
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parameter \WIDTH 1
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connect \CLK \clk
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connect \D 1'0
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connect \Q $q2 [0]
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end
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cell $dff $ff3
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parameter \CLK_POLARITY 1'1
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parameter \WIDTH 2
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connect \CLK \clk
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connect \D 2'00
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connect \Q { $q1 [1] $q2 [1] }
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end
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connect \q [0] $q1 [0]
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connect \q [1] $q2 [0]
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connect \q [2] $q1 [1]
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connect \q [3] $q2 [1]
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end
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EOT
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opt_clean
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opt_merge
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opt_dff
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opt_clean
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