mirror of https://github.com/YosysHQ/yosys.git
95 lines
2.8 KiB
Verilog
95 lines
2.8 KiB
Verilog
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//-----------------------------------------------------
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// This is FSM demo program using function
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// Design Name : fsm_using_function
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// File Name : fsm_using_function.v
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//-----------------------------------------------------
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module fsm_using_function (
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clock , // clock
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reset , // Active high, syn reset
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req_0 , // Request 0
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req_1 , // Request 1
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gnt_0 , // Grant 0
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gnt_1
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);
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//-------------Input Ports-----------------------------
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input clock,reset,req_0,req_1;
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//-------------Output Ports----------------------------
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output gnt_0,gnt_1;
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//-------------Input ports Data Type-------------------
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wire clock,reset,req_0,req_1;
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//-------------Output Ports Data Type------------------
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reg gnt_0,gnt_1;
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//-------------Internal Constants--------------------------
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parameter SIZE = 3 ;
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parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
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//-------------Internal Variables---------------------------
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reg [SIZE-1:0] state ;// Seq part of the FSM
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wire [SIZE-1:0] next_state ;// combo part of FSM
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//----------Code startes Here------------------------
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assign next_state = fsm_function(state, req_0, req_1);
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//----------Function for Combo Logic-----------------
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function [SIZE-1:0] fsm_function;
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input [SIZE-1:0] state ;
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input req_0 ;
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input req_1 ;
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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fsm_function = GNT0;
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end else if (req_1 == 1'b1) begin
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fsm_function= GNT1;
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end else begin
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fsm_function = IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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fsm_function = GNT0;
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end else begin
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fsm_function = IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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fsm_function = GNT1;
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end else begin
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fsm_function = IDLE;
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end
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default : fsm_function = IDLE;
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endcase
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endfunction
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//----------Seq Logic-----------------------------
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always @ (posedge clock)
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begin : FSM_SEQ
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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end else begin
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state <= #1 next_state;
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end
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end
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//----------Output Logic-----------------------------
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always @ (posedge clock)
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begin : OUTPUT_LOGIC
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if (reset == 1'b1) begin
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gnt_0 <= #1 1'b0;
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gnt_1 <= #1 1'b0;
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end
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else begin
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case(state)
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IDLE : begin
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gnt_0 <= #1 1'b0;
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gnt_1 <= #1 1'b0;
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end
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GNT0 : begin
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gnt_0 <= #1 1'b1;
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gnt_1 <= #1 1'b0;
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end
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GNT1 : begin
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gnt_0 <= #1 1'b0;
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gnt_1 <= #1 1'b1;
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end
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default : begin
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gnt_0 <= #1 1'b0;
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gnt_1 <= #1 1'b0;
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end
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endcase
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end
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end // End Of Block OUTPUT_LOGIC
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endmodule // End of Module arbiter
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