mirror of https://github.com/YosysHQ/yosys.git
14 lines
501 B
Plaintext
14 lines
501 B
Plaintext
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:ALU
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select -assert-count 8 t:OBUF
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select -assert-count 8 t:IBUF
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select -assert-count 1 t:GND
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select -assert-count 1 t:VCC
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select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
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