mirror of https://github.com/YosysHQ/yosys.git
41 lines
693 B
Verilog
41 lines
693 B
Verilog
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module testbench;
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reg clk;
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initial begin
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#5 clk = 0;
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forever #5 clk = ~clk;
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end
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wire [15:0] leds;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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$monitor("%b", leds);
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end
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demo uut (
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.clk (clk ),
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`ifdef POST_IMPL
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.\leds[0] (leds[0]),
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.\leds[1] (leds[1]),
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.\leds[2] (leds[2]),
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.\leds[3] (leds[3]),
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.\leds[4] (leds[4]),
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.\leds[5] (leds[5]),
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.\leds[6] (leds[6]),
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.\leds[7] (leds[7]),
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.\leds[8] (leds[8]),
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.\leds[9] (leds[9]),
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.\leds[10] (leds[10]),
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.\leds[11] (leds[11]),
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.\leds[12] (leds[12]),
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.\leds[13] (leds[13]),
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.\leds[14] (leds[14]),
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.\leds[15] (leds[15])
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`else
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.leds(leds)
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`endif
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);
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endmodule
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