mirror of https://github.com/YosysHQ/yosys.git
19 lines
455 B
Plaintext
19 lines
455 B
Plaintext
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read_verilog dpram.v
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
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memory
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opt -full
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# TODO
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#equiv_opt -run prove: -assert null
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
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design -load postopt
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cd top
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select -assert-count 1 t:SB_RAM40_4K
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select -assert-none t:SB_RAM40_4K %% t:* %D
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write_verilog dpram_synth.v
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