mirror of https://github.com/YosysHQ/yosys.git
39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
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/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module uram_ar(data,waddr,we,clk,q);
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parameter d_width = 12;
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parameter addr_width = 2;
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parameter mem_depth = 12;
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input [d_width-1:0] data;
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input [addr_width-1:0] waddr;
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input we, clk;
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output [d_width-1:0] q;
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reg [d_width-1:0] mem [mem_depth-1:0];
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assign q = mem[waddr];
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always @(posedge clk) begin
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if (we)
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mem[waddr] <= data;
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end
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endmodule
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