mirror of https://github.com/YosysHQ/yosys.git
39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
|
/*
|
||
|
|
ISC License
|
||
|
|
|
||
|
|
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||
|
|
|
||
|
|
Permission to use, copy, modify, and/or distribute this software for any
|
||
|
|
purpose with or without fee is hereby granted, provided that the above
|
||
|
|
copyright notice and this permission notice appear in all copies.
|
||
|
|
|
||
|
|
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||
|
|
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||
|
|
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||
|
|
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||
|
|
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||
|
|
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||
|
|
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||
|
|
*/
|
||
|
|
|
||
|
|
module cascade(
|
||
|
|
input signed [5:0] in_A,
|
||
|
|
input signed [4:0] in_B,
|
||
|
|
input signed [4:0] in_D,
|
||
|
|
output signed [11:0] out_P,
|
||
|
|
|
||
|
|
input signed [4:0] casA,
|
||
|
|
input signed [4:0] casB
|
||
|
|
|
||
|
|
);
|
||
|
|
|
||
|
|
wire signed [9:0] cascade;
|
||
|
|
// first dsp
|
||
|
|
assign cascade = casA * casB;
|
||
|
|
|
||
|
|
// second dsp
|
||
|
|
assign out_P = in_A * (in_B + in_D) + cascade;
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|