mirror of https://github.com/YosysHQ/yosys.git
19 lines
254 B
Plaintext
19 lines
254 B
Plaintext
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read_verilog <<EOT
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module uut(
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input [3:0] a, b,
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output [3:0] y, z
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);
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assign y = a + b;
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assign z = b + a;
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endmodule
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EOT
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copy uut after
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opt_merge after
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clean
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show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
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