mirror of https://github.com/YosysHQ/yosys.git
49 lines
811 B
Plaintext
49 lines
811 B
Plaintext
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read_verilog <<EOT
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module top(...);
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input [7:0] wa;
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input [7:0] ra1;
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input [7:0] ra2;
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input [7:0] wd;
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input clk;
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wire [7:0] rd1;
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wire [7:0] rd2;
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reg [7:0] mem[0:7];
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always @(posedge clk)
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mem[wa] <= wd;
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assign rd1 = mem[ra1];
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assign rd2 = mem[ra2];
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initial mem[8'h12] = 8'h34;
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endmodule
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EOT
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proc
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select -assert-count 2 t:$memrd
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select -assert-count 1 t:$memwr
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select -assert-count 1 t:$meminit
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design -save orig
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opt_clean
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select -assert-none t:$memrd
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select -assert-none t:$memwr
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select -assert-none t:$meminit
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design -load orig
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expose top/rd1
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opt_clean
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select -assert-count 1 t:$memrd
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select -assert-count 1 t:$memwr
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select -assert-count 1 t:$meminit
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design -load orig
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expose top/rd1 top/rd2
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opt_clean
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select -assert-count 2 t:$memrd
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select -assert-count 1 t:$memwr
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select -assert-count 1 t:$meminit
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