mirror of https://github.com/YosysHQ/yosys.git
12 lines
416 B
Coq
12 lines
416 B
Coq
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module demo (
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input clk,
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output led1, led2, led3, led4, led5, led6, led7, led8,
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output led9, led10, led11, led12, led13, led14, led15, led16
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);
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localparam PRESCALE = 20;
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reg [PRESCALE+3:0] counter = 0;
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always @(posedge clk) counter <= counter + 1;
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assign {led1, led2, led3, led4, led5, led6, led7, led8,
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led9, led10, led11, led12, led13, led14, led15, led16} = 1 << counter[PRESCALE +: 4];
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endmodule
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