mirror of https://github.com/YosysHQ/yosys.git
11 lines
170 B
Verilog
11 lines
170 B
Verilog
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module uut_always01(clock, reset, count);
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input clock, reset;
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output [3:0] count;
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reg [3:0] count;
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always @(posedge clock)
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count <= reset ? 0 : count + 1;
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endmodule
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