2019-06-24 23:52:53 -05:00
|
|
|
read_verilog abc9.v
|
2019-07-02 21:13:40 -05:00
|
|
|
design -save read
|
|
|
|
|
hierarchy -top abc9_test027
|
2019-06-24 23:52:53 -05:00
|
|
|
proc
|
|
|
|
|
design -save gold
|
|
|
|
|
|
|
|
|
|
abc9 -lut 4
|
|
|
|
|
check
|
|
|
|
|
design -stash gate
|
|
|
|
|
|
|
|
|
|
design -import gold -as gold
|
|
|
|
|
design -import gate -as gate
|
|
|
|
|
|
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
|
|
|
sat -verify -prove-asserts -show-ports miter
|
|
|
|
|
|
2019-07-02 21:13:40 -05:00
|
|
|
design -load read
|
|
|
|
|
hierarchy -top abc9_test028
|
|
|
|
|
proc
|
|
|
|
|
|
|
|
|
|
abc9 -lut 4
|
2019-07-12 23:00:13 -05:00
|
|
|
select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
|
2019-07-02 21:13:40 -05:00
|
|
|
select -assert-count 1 t:unknown
|
|
|
|
|
select -assert-none t:$lut t:unknown %% t: %D
|
