yosys/techlibs/nexus/lutrams_map.v

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Verilog
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module $__NEXUS_DPR16X4_ (...);
parameter INIT = 64'b0;
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input PORT_W_CLK;
input [3:0] PORT_W_ADDR;
input [3:0] PORT_W_WR_DATA;
input PORT_W_WR_EN;
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input [3:0] PORT_R_ADDR;
output [3:0] PORT_R_RD_DATA;
DPR16X4 #(
.INITVAL($sformatf("0x%08x", INIT))
) _TECHMAP_REPLACE_ (
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.RAD(PORT_R_ADDR),
.DO(PORT_R_RD_DATA),
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.WAD(PORT_W_ADDR),
.DI(PORT_W_WR_DATA),
.WCK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
endmodule