mirror of https://github.com/YosysHQ/yosys.git
16 lines
319 B
Verilog
16 lines
319 B
Verilog
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module constpower(ys, yu);
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output [8*8*8-1:0] ys, yu;
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genvar i, j;
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generate
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for (i = 0; i < 8; i = i+1)
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for (j = 0; j < 8; j = j+1) begin:V
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assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4);
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assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j);
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end
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endgenerate
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endmodule
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