mirror of https://github.com/YosysHQ/yosys.git
25 lines
493 B
Verilog
25 lines
493 B
Verilog
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// test taken from aes_core from iwls2005
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module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
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input clk, kld;
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input [15:0] key;
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output [3:0] wo_0, wo_1, wo_2, wo_3;
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reg [3:0] w[3:0];
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assign wo_0 = w[0];
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assign wo_1 = w[1];
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assign wo_2 = w[2];
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assign wo_3 = w[3];
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always @(posedge clk) begin
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w[0] <= kld ? key[15:12] : w[0];
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w[1] <= kld ? key[11: 8] : w[0]^w[1];
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w[2] <= kld ? key[ 7: 4] : w[0]^w[1]^w[2];
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w[3] <= kld ? key[ 3: 0] : w[0]^w[1]^w[2]^w[3];
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end
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endmodule
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