mirror of https://github.com/YosysHQ/yosys.git
35 lines
537 B
Verilog
35 lines
537 B
Verilog
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module \$__NEXUS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter [63:0] INIT = 64'b0;
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parameter CLKPOL2 = 1;
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input CLK1;
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input [3:0] A1ADDR;
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output [3:0] A1DATA;
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input [3:0] B1ADDR;
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input [3:0] B1DATA;
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input B1EN;
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wire wck;
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generate
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if (CLKPOL2)
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assign wck = CLK1;
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else
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INV wck_inv_i (.A(CLK1), .Z(wck));
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endgenerate
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DPR16X4 #(
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.INITVAL($sformatf("0x%08x", INIT))
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) _TECHMAP_REPLACE_ (
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.RAD(A1ADDR),
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.DO(A1DATA),
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.WAD(B1ADDR),
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.DI(B1DATA),
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.WCK(CLK1),
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.WRE(B1EN)
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);
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endmodule
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