2024-11-04 17:36:31 -06:00
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read_rtlil << EOT
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2022-05-18 14:20:42 -05:00
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module \top
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wire width 4 input 0 \S
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wire width 5 output 1 \Y
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cell $bmux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 4
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connect \A 80'10110100011101110001110010001110101010111000110011111111111110100000110100111000
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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hierarchy -auto-top
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design -save preopt
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memory_bmux2rom
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select -assert-count 1 t:$memrd_v2
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memory_map
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opt_dff
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design -stash postopt
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equiv_opt -assert -run prepare: dummy
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